As is well known, semiconductor manufacturing processes, as used to manufacture integrated circuits (ICs), involve a succession of fabrication operations requiring accurate registration of the tools used in each operation with the semiconductor wafer being processed. More specifically, successful semiconductor manufacturing requires highly accurate alignment of features on masks used in photolithographic processes, such that overlying successive mask-defined patterns of material are located on the wafer with accuracy in the low tens of nanometers range. Lithographic tools with such capabilities are being developed, but the metrology to routinely monitor and evaluate the performance of these new tools is lagging. Specifically, electrical test structures--that is, structures formed using the same tools and techniques used to manufacture the product of interest, but designed to have known and readily measurable characteristics, to allow evaluation of the manufacturing process--are needed. See Buehler et al U.S. Pat. Nos. 4,516,071 and 4,918,377, and Thomas U.S. Pat. No. 3,974,443, providing low-cost test structures for evaluating the accuracy of manufacturing steps during the advanced stages of process development and during manufacturing. However, the test structures shown in these documents are inadequate to meet current needs.
There are three principal classes of applications of test structures of interest here. In a first class of application, where the test structure is used for evaluation of accuracy of pattern generation feature placement, the entire test structure is replicated in a single conducting film on the substrate after it is imaged by a steered beam and then developed in an overlying resist film. When, for example, the serial printing of the features of the test structure during manufacture is interrupted by repositioning of the workpiece with respect to the printing equipment, the test structure allows the evaluation of the accuracy of placement of the features printed prior to the interruption with respect to those printed subsequently. The extracted relative placement of local features enables comparison with their specified relative placement. This comparison provides a significant figure of merit for pattern generation tool performance evaluation.
In a second class of applications, where the test structure is used to evaluate overlay extraction for tool alignment capability evaluation, and for mapping the local overlay (i.e., mismatch) of features on a pair of masks, two different complementary patterns, together constituting the test structure, are exposed with the same tool into the same single resist film prior to development of the composite image and its replication in an underlying conducting film. The test structure enables measurement of any local mismatch in the overlay of the two exposures. If, for example, the two exposures are made using two respective masks, and the contributions to the observed overlay originating in the patterning of the masks are known or are insignificant, then the tool alignment performance may be extracted. Conversely, when the tool-induced contribution to overlay is insignificant or is separately extracted, then the local overlay of the two masks can be measured. When the location of features in the resist by the first mask defines a reference grid, overlay mapping then enables the evaluation of feature placement on the second mask, which may be an x-ray lithography reticle, for example.
A third class of applications, where the test structure is used for mapping the local overlay of two levels in a standard or nonstandard IC wafer fabrication process, involves measurement of the alignment of features on a mask to those on a substrate that is pre-patterned with a conducting film. An important application is measuring the alignment of vias (i.e., holes extending through an insulating layer or the like) with respect to an underlying metal interconnect layer. The process used to fabricate the test structure typically includes at least two separate etch and two separate photolithographic steps. However, the entire test structure may still be replicated in a single conducting film which is patterned twice. See J. J. LaBrie, B. Fay, M. A. Blanco, K. M. Monahan, J. T. Chen, D. F. Kyser, "Characterization of Two Level Overlay in X-Ray/Optical Stepper Mix and Match Lithography", SPIE Vol. 775, Integrated Circuit Metrology, Inspection, and Process Control (1987).
The prior art includes numerous electrical test structures useful in one or more of the classes of applications described above. A first type of electrical test structure, termed the "differential linewidth bridge" or "cross-bridge resistor" has been used for measurement of electrical linewidth. See U.S. Pat. No. 3,974,443 to Thomas, and U.S. Pat. No. 4,516,071 to Buehler, and M. G. Buehler, S. D. Grant, and W. R. Thurber, "Bridge and van der Pauw Sheet Resistors for Characterizing the Linewidths of Conducting Layers", J. Electrochem. Soc., Vol. 125, pp. 650-654 (1978). Using a differential linewidth bridge for overlay measurement enables the extraction and mapping of the local overlay of two patterns from the difference in linewidth of a pair of closely separated, parallel, linear features. The respective features are replicated on the substrate by splitting lengthwise, with a second exposure, a single linear feature defined by a first exposure.
An example of the steps used in forming such a split bridge test structure is shown in FIG. 1. FIG. 1(a) shows a first pattern, e.g., used to form conductive material on a substrate. FIG. 1(b) shows a second similar pattern used similarly. If the two patterns are properly aligned, the pattern of FIG. 1(c) results. To test the relative alignment, currents can be forced between the conductive pads 10 of the lower pattern and 12 of the upper pattern by applying test voltages therebetween. If the two exposures were properly aligned, the conductors 14 and 16 connecting the pads 10 and 12, respectively, will be of equal width, and hence will conduct equal current.
Using this technique, Y. Kuroki, S. Hasegawa, T. Honda, and Y. Iida, "X-ray Exposure Mask Accuracy Evaluation Using Electrical Test Structures", Proc. IEEE International Conference on Microelectronic Test Structures, Vol. 4, No. 1, 123-127, March 1991 report resolutions of better than 100 nm in overlay metrology in double mask processing. B. Fay and T. Hasan, "Electrical Measurement Techniques for the Characterization of X-Ray Lithography Systems", Solid State Technology, pp. 239-243, May 1986 and C. J. Ashton, "Differential Linewidth Structures for overlay Measurements at 0.25 Micron Ground Rules", SPIE Vol. 775, Integrated Circuit Metrology, Inspection and Process Control, p. 201 (1987) demonstrate comparable results in a single conducting film.
However, there are limitations on use of this technique. Its use for the first class of applications discussed above is technically cumbersome, and it is process-incompatible with the third class of applications. of course, it may still be used in multilevel applications where a nonstandard IC fabrication process sequence is acceptable. The differential linewidth bridge technique can also be used to evaluate manufacturing techniques in the second class of applications discussed above, although there the two complementary patterns must be imaged in positive resist.
A second significant limitation of the differential linewidth bridge technique is that the evaluation of the accuracy of placement, that is, the accuracy of the overlay of successive operations, is only as accurate as the linewidth measurement. More specifically, in conductors having smaller dimensions, the distinction between the actual or "physical" linewidth of a tap connected to a principal conductor and its measured or "electrical" linewidth becomes significant. In uniform films, the correspondence between physical and electrical linewidths tends to be very good even into the submicrometer region. It is not necessary to use test structures having submicrometer geometries when measuring comparative linewidths for the purpose of determining overlay. In fact, submicrometer linewidths may actually be deleterious in this application because what is actually extracted in a linewidth bridge measurement is the average electrical linewidth along the length of the bridge. This length is typically at least 100 .mu.m. The relationship of this extracted average to the variation in the actual local linewidth at different points along its length, as a consequence of material and/or processing nonuniformities, is significant. The smaller the area occupied by the test structure, the more sensitive is the extracted measurement to the effective spatial resolution. That is, the accuracy of a measurement of overlay mismatch in, for example, the x-direction, made using the differential linewidth technique, is affected by any mismatch in the y-direction. Further, the effect of mismatches in one dimension on measurements of mismatches in the other dimension increases with the minimum size of the basic structure.
A second well-known test structure used in evaluation of IC manufacturing techniques is the van der Pauw bridge shown in FIGS. 2(a)-(c). As in the case of the differential linewidth bridge of FIGS. 1(a)-(c), FIGS. 2(a) and (b) show two patterns printed in successive operations. If they are aligned correctly, the symmetrical structure of FIG. 2(c) is formed in conductive material. Its symmetry can be determined by forcing currents between various pairs of the pads 20; if uniform current flows between each pair, the two exposures were properly aligned.
Until recently, the van der Pauw resistor alignment bridge shown in FIGS. 2(a)-(c) had been used exclusively in the first and second classes of applications in which the complementary patterns were sequentially imaged in negative resist, that is, at least when the conducting film was patterned by etching. See D. S. Perloff, "A Van der Pauw Resistor Structure for Determining Mask Superposition Errors on Semiconductor Slices", Solid State Electronics 21, pp. 1013-1018 (1978). However, a more recent paper has reported on the extension of its use to a multilevel structure of the third class of application. D. W. Feldbaumer, C. J. Varker, M. Griswold, and B. J. Allen, "Design and Application of the Interlayer van der Pauw Resistor Alignment Bridge", IEEE Transactions on Semiconductor Manufacturing, Vol. 3, No. 4, pp. 206-215, November 1990. In all applications, the van der Pauw bridge offers compactness of the active area for pairs of measurements in both coordinate directions. Another advantage is that the multilevel implementation is fully IC process-compatible.
However, the absolute accuracy and precision provided by the van der Pauw bridge are comparable to that provided by other techniques only when applied to films of relatively high sheet resistivity .rho..sub.s. In particular, in-depth analyses provided by Perloff, supra, suggest that .rho..sub.s greater than 100 .OMEGA./sq may be necessary to reduce measurement uncertainties to below about 20 nm, for example. Both sensitivity (mV/.mu.m) and accuracy degrade as .rho..sub.s decreases. Accordingly, the application of this structure to the low sheet resistivity films used for interconnect metal could be quite difficult.
FIG. 3 reviews the salient features of the basic architecture of a third principal type of known test structure, the voltage-dividing potentiometer disclosed in D. R. Thomas and Richard D. Presson, "An Electrical Photolithographic Alignment Monitor", Digest of Papers, Government Microcircuit Applications Conference, pp. 196-197 (1974) and T. J. Russell, T. F. Leedy, and R. L. Mattis, "A Comparison of Electrical and Visual Test Structures For Evaluating Photomask Alignment in Integrated Circuit Manufacturing", Technical Digest IEDM, Washington, D.C., pp. 1-3, Dec. 5-7, 1977. Such a potentiometer provides a measurement of the displacement of a central "tap" or probe P1 between two end taps P2 and P3. If P1 is formed in a separate operation than that used to form P2 and P3, the potentiometer provides an indication of the accuracy of the alignment of the operations.
The basic test structure architecture shown in FIG. 3 is referred to herein as the "classical" voltage-dividing potentiometer. The Thomas et al and Russell et al papers, supra, describe the performance of such potentiometer-based test structures. In both cases, the reported measurement uncertainties were approximately 100 nm.
The classical voltage dividing potentiometer provided by FIG. 3 is used by forcing a current to flow between the ends of a "bridge conductor" 22, and measuring the voltage drops V.sub.1 and V.sub.2 between pairs of taps 24 and 26, and 24 and 28, respectively. Comparison of V.sub.1 and V.sub.2 indicates the relative resistance of the corresponding portions of the segment of bridge 22 between taps 26 and 28 and hence of their relative length. The "offset" x of the probe P1 as it "slides" along the bridge conductor 22, relative to the midpoint between probes P2 and P3, is determined from the relationship between the voltage drops V.sub.1 and V.sub.2, and the distances x and L, as a test current is forced through the bridge, according to: ##EQU1##
When the structure is implemented on IC wafers (for example), the probe P1 is referred to as the "center" tap 24, and the probes P2 and P3 are referred to as "end" taps 26 and 28. The center-to-center spacing of taps 26 and 28, L, serves as the reference length or "ruler" for the measurement of x, the "offset" of the probe P1 from the midpoint of probes P2 and P3.
The voltage-dividing potentiometer, including the enhanced version according to the invention that is described below, is readily implemented for the first, second and third classes of applications.
In order that measurements made using a voltage dividing potentiometer and analyzed according to Eq. (1) can provide a correct measurement for the offset x, that is, in order to evaluate correctly the accuracy of registration of successive manufacturing operations (for example), the taps must be electrically connected to the bridge at point contacts. If the taps are not thus connected to the bridge by point contacts, systematic errors in the extracted value of x will result from an effective shortening of the electrical bridge length due to the finite width of the contact regions connecting the taps to the bridge. The bridge can be made sufficiently long that the tap contacts are essentially point contacts relative to the bridge's length. In this limiting case, the quantity L may be approximated by Eq. (1) as the design value of the center-to-center separations of the end taps. However, when this approach is taken, random errors resulting from the extended length of the bridge, combined with micro-scale variations of the test structure composition and geometry and voltage measurement noise, limit the classical voltage-dividing potentiometer to about 0.1 .mu.m resolution. Further, in many circumstances it is impractical to significantly extend the bridge conductor 22 to provide a large value for L.
Since the filing of parent application Ser. No. 07/852,439, (U.S. Pat. No. 5,383,136) it has been realized that errors from a number of different sources may arise during microcircuit fabrication, all resulting in improper evaluation of conductor lengths of conducting segments when determined by voltage drops across them. It would be desirable to provide a test structure whereby these various sources of error in conductor length measurements might be distinguished from one another.
For example, the art is generally aware of systematic patterning errors referred to collectively as "overlay." The "overlay" O is a vector quantity defined at every location on the substrate as the difference between the vector position P.sub.1 of (for example) a first portion of a conductive structure on a substrate with respect to an arbitrary reference point, and the vector position of the corresponding point P.sub.2 in an overlaying pattern, e.g., a second portion of the conductive structure. The overly O is zero when P.sub.1 =P.sub.2, i.e., when the composite pattern is formed correctly. For example, patterning overlay errors result when the features formed on a substrate in a second image-transfer operation are not properly located relative to features having been formed thereon in a prior operation, in which case the "overlay" has a nonzero value; nonzero overlay may also result when a feature is improperly located with respect to other features formed in the same imaging operation. Thus, nonzero "overlay" (as the term is used by the art) may derive from the misalignment of images formed sequentially by the image-transfer tooling, e.g., when two or more masks are used in sequential photolithography operations to form a resulting composite pattern on the substrate. Nonzero "overlay" may also result from errors or defects in one or more of the masks, e.g., improper placement of features on the masks.
In the parent application, a quantity "x", referred to as the "offset", was defined to be the displacement of the center tap of a potentiometer formed on a substrate in a second image-transfer operation from the midpoint between the two end taps of the potentiometer formed thereon in a prior image-transfer operation. When the displacement x was zero, the composite pattern was defined to have zero overlay. Thus the displacement x measured using the potentiometer in many cases corresponded to the overly O of the overlaying patterns forming the composite pattern, that is, when the overly O was due entirely to an error measured by the offset x. While for such potentiometers the offset x of an individual potentiometer may or may not be defined to be the same as the overly O of the composite pattern, the difference between the values of x and O will be constant in foreseeable applications. For example, when the composite pattern includes two or more potentiometers formed in the same image-transfer operations, they may exhibit different displacements x.sub.1 and x.sub.2, but the overlay of the composite pattern will be the same.
Microcircuit fabrication processes used to form individual or composite patterns are also susceptible to random errors caused by patterning microdefects. These may affect the reliability of overlay measurements derived from estimates of the quantity x defined previously.
The inventors have also found that corners intended to be square where conductive features meet on a substrate tend to be rounded at their inside corners, potentially contributing further errors in measurement of respective conductor lengths.
It would be highly desirable to provide a test structure from which overlay could be extracted electrically in a manner which minimized the effects of patterning microdefects through redundancy afforded by the formation of multiple potentiometers located at a single site, separated the overlay measurements into contributions deriving from feature misplacement on the masks and from misalignment of portions of composite images formed using more than one mask, and provided integral facilities for estimation of overlay introduced by imaging tools. One purpose of the last-mentioned facility would be to enable cross-referencing electrical and imaging-tool measurements of the overlay embedded in a single composite pattern.
Identification of the various sources of errors in conductor length measurements would also be useful for improvement of process quality and increasing yields of manufacturing processes.
It is common in the semiconductor manufacturing industry, and other industries, to provide a line scale, that is, a physical ruler, having divisions to allow measurement of lengths by optical comparison. Line scales are commonly provided as part of a microscope stage, in the eyepiece of a microscope, or elsewhere, for convenient measurement of features on semiconductor wafers and the like. It is currently not convenient to calibrate such line scales against an absolute length standard, such as the line scale interferometer maintained by the National Institute of Standards and Technology, assignee of the present application. It would be desirable to provide a convenient method of calibration of line scales against such an absolute length reference.